An encryption processing circuit capable of inhibiting leakage of secret information from bit transitions of a register while inhibiting an increase in performance/area ratio is provided.N (N is an integer equal to 2 or greater) sets, each of which including an encryption block and a register, are included, wherein an encryption block of an i-th set performs encryption in a certain step on plain text stored in the register of the i-th set or intermediate data stored in the register of the i-th set obtained from the plain text and the intermediate data obtained by the encryption is stored in the register of an (i+1)-th set and the encryption block of an N-th set performs the encryption in the certain step on plain text stored in the register of the N-th set or intermediate data stored in the register of the N-th set obtained from the plain text and the intermediate data obtained by the encryption is stored in the register of a first set.