Methods for monitoring one or more load currents corresponding with one or more voltage regulators used during operation of a semiconductor memory are described. The one or more load currents may be due to the biasing of memory cells within a memory array or due to the presence of shorts between lines in the memory array. A plurality of load currents corresponding with a plurality of voltage regulators may be monitored in real-time before and during biasing of one or more memory arrays. The plurality of load currents may be monitored using a configurable load current monitoring circuit that uses a current summation technique. The ability to monitor the plurality of load currents before performing a programming operation on a memory array allows for remapping of defective portions of the memory array and modification of programming bandwidth prior to the programming operation.