Invention Grant
- Patent Title: Stacked semiconductor chips having double adhesive insulating layer interposed therebetween
- Patent Title (中): 具有双层粘合绝缘层的堆叠半导体芯片
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Application No.: US12071628Application Date: 2008-02-25
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Publication No.: US08841776B2Publication Date: 2014-09-23
- Inventor: Takao Nishimura , Yoshiaki Narisawa
- Applicant: Takao Nishimura , Yoshiaki Narisawa
- Applicant Address: JP Yokohama
- Assignee: Fujitsu Semiconductor Limited
- Current Assignee: Fujitsu Semiconductor Limited
- Current Assignee Address: JP Yokohama
- Agency: Westerman, Hattori, Daniels & Adrian, LLP
- Priority: JP2005-242780 20050824
- Main IPC: H01L25/065
- IPC: H01L25/065

Abstract:
In a semiconductor chip, a first semiconductor chip 21 is provided on a chip-mounting component 11, and bonding wires 36 connected to electrode pads 21E of the first semiconductor chip 21 are fixed by being covered with a first insulating adhesive 31. A second semiconductor chip 22 is mounted by being stacked on the first semiconductor chip 21, with the first insulating adhesive 31 therebetween. This structure can prevent problems such as breaking and short-circuits of bonding wires of the chip disposed directly on a substrate when another chip is mounted by being stacked.
Public/Granted literature
- US20080150120A1 Semiconductor device and method of producing the same Public/Granted day:2008-06-26
Information query
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