Invention Grant
- Patent Title: Semiconductor package and manufacturing method thereof
- Patent Title (中): 半导体封装及其制造方法
-
Application No.: US12439257Application Date: 2007-12-18
-
Publication No.: US08841759B2Publication Date: 2014-09-23
- Inventor: Kyung Joo Son
- Applicant: Kyung Joo Son
- Applicant Address: KR Seoul
- Assignee: LG Innotek Co., Ltd.
- Current Assignee: LG Innotek Co., Ltd.
- Current Assignee Address: KR Seoul
- Agency: Saliwanchik, Lloyd & Eisenschenk
- Priority: KR10-2006-0133279 20061223; KR10-2007-0009661 20070130
- International Application: PCT/KR2007/006620 WO 20071218
- International Announcement: WO2008/078899 WO 20080703
- Main IPC: H01L23/02
- IPC: H01L23/02 ; H01L23/498 ; H01L25/10 ; H01L23/31 ; H01L21/56 ; H01L23/00

Abstract:
Provided are a semiconductor package and a manufacturing method thereof. A semiconductor package according to an embodiment comprises a chip part on a board, a mold member, and a plated layer on the mold member. The plated layer comprises an electrode pattern connected to a pattern of the board. The electrode pattern of the plated layer can be mounted at least one of at least one a chip part and at least one another semiconductor package.
Public/Granted literature
- US20090321911A1 Semiconductor Package and Manufacturing Method Thereof Public/Granted day:2009-12-31
Information query
IPC分类: