Systems and methods for performing static timing analysis during IC design. A method is provided that includes obtaining canonical input data. The method further includes calculating at least one input condition identifier based on the canonical input data. The method further includes comparing the at least one input condition identifier to a table of values. The method further includes that when a match exists between the at least one input condition identifier and at least one value within the table of values, retrieving previously calculated timing data associated with the at least one value, and applying the previously calculated timing data in a timing model for a design under timing analysis.