Technologies are generally described for exploiting program phase behavior to duplicate most recently and/or frequently accessed tag entries in a Tag Replication Buffer (TRB) to protect the information integrity of tag arrays in a processor cache. The reliability/effectiveness of microprocessor cache performance may be further improved by capturing/duplicating tags of dirty cache lines, exploiting the fact that detected error-corrupted clean cache lines can be recovered by L2 cache. A deterministic TRB replacement triggered early write-back scheme may provide full duplication and recovery of single-bit errors for tags of dirty cache lines.