Invention Grant
- Patent Title: Semiconductor memory device
- Patent Title (中): 半导体存储器件
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Application No.: US13865011Application Date: 2013-04-17
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Publication No.: US08830774B2Publication Date: 2014-09-09
- Inventor: Naoki Kuroda
- Applicant: Panasonic Corporation
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2010-280989 20101216
- Main IPC: G11C7/02
- IPC: G11C7/02 ; G11C7/06 ; G11C11/419 ; G11C7/18 ; G11C7/12

Abstract:
In a static random access memory (SRAM) device having a hierarchical bit line architecture, a local sense amplifier (SA) circuit includes P-channel transistors which precharge local bit lines connected to memory cells, P-channel transistors each having a gate connected to a corresponding one of the local bit lines and a drain connected to a corresponding one of global bit lines, and N-channel transistors each having a gate connected to a corresponding one of the global bit lines and a drain connected to a corresponding one of the local bit lines. As a result, restore operation to a non-selected memory cell during write operation can be achieved without the need of a fine timing control, the speed of read operation by a feedback function can be increased, and the area can be reduced.
Public/Granted literature
- US20130229887A1 SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2013-09-05
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