Invention Grant
- Patent Title: Sigma-delta ADC with test circuitry
- Patent Title (中): 带有测试电路的Σ-ΔADC
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Application No.: US13807632Application Date: 2011-06-28
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Publication No.: US08830098B2Publication Date: 2014-09-09
- Inventor: Salvador Mir , Haralampos Stratigopoulos , Matthieu Dubois
- Applicant: Salvador Mir , Haralampos Stratigopoulos , Matthieu Dubois
- Applicant Address: CH Genève
- Assignee: STMicroelectronics International NV
- Current Assignee: STMicroelectronics International NV
- Current Assignee Address: CH Genève
- Agency: Kaplan Breyer Schwarz & Ottesen, LLP
- Priority: FR1002741 20100630
- International Application: PCT/EP2011/060863 WO 20110628
- International Announcement: WO2012/001019 WO 20120105
- Main IPC: H03M3/00
- IPC: H03M3/00

Abstract:
The invention concerns a sigma-delta switched capacitor analog to digital converter (ADC) having: an input line for receiving a signal to be converted; first, second and third inputs for respectively receiving first, second and third test voltages; and switching circuitry adapted to apply, during a test mode of the sigma-delta ADC, a ternary test signal to the input line by periodically selecting, based on a digital test control signal, one of the first, second or third test voltages to be applied to the input line.
Public/Granted literature
- US20130201046A1 SIGMA-DELTA ADC WITH TEST CIRCUITRY Public/Granted day:2013-08-08
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