Invention Grant
US08829965B2 System and method to perform scan testing using a pulse latch with a blocking gate
有权
使用具有阻塞门的脉冲锁存器执行扫描测试的系统和方法
- Patent Title: System and method to perform scan testing using a pulse latch with a blocking gate
- Patent Title (中): 使用具有阻塞门的脉冲锁存器执行扫描测试的系统和方法
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Application No.: US13564254Application Date: 2012-08-01
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Publication No.: US08829965B2Publication Date: 2014-09-09
- Inventor: Venkatasubramanian Narayanan , Kashyap R. Bellur
- Applicant: Venkatasubramanian Narayanan , Kashyap R. Bellur
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agent Paul S. Holdaway
- Main IPC: H03K3/356
- IPC: H03K3/356

Abstract:
A system and method to perform scan testing using a pulse latch with a blocking gate is disclosed. In a particular embodiment, a scan latch includes a pulse latch operable to receive data while a pulse clock signal has a first logical clock value and a blocking gate coupled to an output of the pulse latch. The blocking gate is operable to propagate the data from the output of the pulse latch while the pulse clock signal has a second logical clock value.
Public/Granted literature
- US20140035645A1 SYSTEM AND METHOD TO PERFORM SCAN TESTING USING A PULSE LATCH WITH A BLOCKING GATE Public/Granted day:2014-02-06
Information query
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