Invention Grant
- Patent Title: No pin test mode
- Patent Title (中): 无引脚测试模式
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Application No.: US13188802Application Date: 2011-07-22
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Publication No.: US08829932B2Publication Date: 2014-09-09
- Inventor: John R. Turner , Nathan Charland
- Applicant: John R. Turner , Nathan Charland
- Applicant Address: US CA San Jose
- Assignee: Fairchild Semiconductor Corporation
- Current Assignee: Fairchild Semiconductor Corporation
- Current Assignee Address: US CA San Jose
- Agency: Schwegman, Lundberg & Woessner, P.A.
- Main IPC: G01R31/3187
- IPC: G01R31/3187 ; G01R31/28 ; G01R31/317

Abstract:
This application provides apparatus and methods for initiating tests in an interface circuit without using inputs of the interface circuit dedicated to initiating the tests. In an example, a test mode interface circuit can include a voltage comparator configured compare a first voltage to a second voltage, a ripple counter configured to count pulses from a processor when the voltage comparator indicates that the first voltage is greater than the second voltage, and wherein the test mode interface circuit is configured to provide a test mode enable signal and an indication of the a desired test mode an interface circuit that includes the test mode interface circuit.
Public/Granted literature
- US20120019273A1 NO PIN TEST MODE Public/Granted day:2012-01-26
Information query
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