Invention Grant
- Patent Title: Integrated circuit 3D memory array and manufacturing method
- Patent Title (中): 集成电路3D存储阵列及制造方法
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Application No.: US12430290Application Date: 2009-04-27
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Publication No.: US08829646B2Publication Date: 2014-09-09
- Inventor: Hsiang-Lan Lung , Hang-Ting Lue
- Applicant: Hsiang-Lan Lung , Hang-Ting Lue
- Applicant Address: TW Hsinchu
- Assignee: Macronix International Co., Ltd.
- Current Assignee: Macronix International Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes Beffel & Wolfeld LLP
- Main IPC: H01L23/52
- IPC: H01L23/52 ; H01L27/102 ; H01L27/10 ; H01L27/112
Abstract:
A 3D memory device is based on an array of electrode pillars and a plurality of electrode planes that intersect the electrode pillars at interface regions that include memory elements that comprise a programmable element and a rectifier. The electrode pillars can be selected using two-dimensional decoding, and the plurality of electrode planes can be selected using decoding on a third dimension.
Public/Granted literature
- US20100270593A1 INTEGRATED CIRCUIT 3D MEMORY ARRAY AND MANUFACTURING METHOD Public/Granted day:2010-10-28
Information query
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