Invention Grant
US08829610B2 Method for forming semiconductor layout patterns, semiconductor layout patterns, and semiconductor structure
有权
用于形成半导体布局图案，半导体布局图案和半导体结构的方法
- Patent Title: Method for forming semiconductor layout patterns, semiconductor layout patterns, and semiconductor structure
- Patent Title (中): 用于形成半导体布局图案，半导体布局图案和半导体结构的方法
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Application No.: US13471468Application Date: 2012-05-15
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Publication No.: US08829610B2Publication Date: 2014-09-09
- Inventor: Jie Zhao , Huabiao Wu
- Applicant: Jie Zhao , Huabiao Wu
- Applicant Address: TW Science-Based Industrial Park, Hsin-Chu
- Assignee: United Microelectronics Corp.
- Current Assignee: United Microelectronics Corp.
- Current Assignee Address: TW Science-Based Industrial Park, Hsin-Chu
- Agent Winston Hsu; Scott Margo
- Main IPC: H01L29/66
- IPC: H01L29/66
Abstract:
A method for forming semiconductor layout patterns providing a pair of first layout patterns being symmetrical along an axial line, each of the first layout patterns comprising a first side proximal to the axial line and a second side far from the axial line; shifting a portion of the first layout patterns toward a direction opposite to the axial line to form at least a first shifted portion in each first layout pattern, and outputting the first layout patterns and the first shifted portions on a first mask.
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Information query
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