Invention Grant
- Patent Title: Reducing variation by using combination epitaxy growth
- Patent Title (中): 通过组合外延生长减少变异
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Application No.: US13030850Application Date: 2011-02-18
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Publication No.: US08828850B2Publication Date: 2014-09-09
- Inventor: Yu-Hung Cheng , Chii-Horng Li , Tze-Liang Lee , Yi-Hung Lin
- Applicant: Yu-Hung Cheng , Chii-Horng Li , Tze-Liang Lee , Yi-Hung Lin
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater and Matsil, L.L.P.
- Main IPC: H01L21/20
- IPC: H01L21/20 ; H01L21/36

Abstract:
A method for forming a semiconductor structure includes forming a gate stack over a semiconductor substrate in a wafer; forming a recess in the semiconductor substrate and adjacent the gate stack; and performing a selective epitaxial growth to grow a semiconductor material in the recess to form an epitaxy region. The step of performing the selective epitaxial growth includes performing a first growth stage with a first growth-to-etching (E/G) ratio of process gases used in the first growth stage; and performing a second growth stage with a second E/G ratio of process gases used in the second growth stage different from the first E/G ratio.
Public/Granted literature
- US20110287611A1 Reducing Variation by Using Combination Epitaxy Growth Public/Granted day:2011-11-24
Information query
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