Invention Grant
- Patent Title: MOSFET including asymmetric source and drain regions
-
Application No.: US14200800Application Date: 2014-03-07
-
Publication No.: US08828828B2Publication Date: 2014-09-09
- Inventor: Kangguo Cheng , Balasubramanian S. Haran , Shom Ponoth , Theodorus E. Standaert , Tenko Yamashita
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent Joseph Petrokaitis, Esq.
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L29/66

Abstract:
At least one drain-side surfaces of a field effect transistor (FET) structure, which can be a structure for a planar FET or a fin FET, is structurally damaged by an angled ion implantation of inert or electrically active dopants, while at least one source-side surface of the transistor is protected from implantation by a gate stack and a gate spacer. Epitaxial growth of a semiconductor material is retarded on the at least one structurally damaged drain-side surface, while epitaxial growth proceeds without retardation on the at least one source-side surface. A raised epitaxial source region has a greater thickness than a raised epitaxial drain region, thereby providing an asymmetric FET having lesser source-side external resistance than drain-side external resistance, and having lesser drain-side overlap capacitance than source-side overlap capacitance.
Public/Granted literature
- US20140187007A1 MOSFET INCLUDING ASYMMETRIC SOURCE AND DRAIN REGIONS Public/Granted day:2014-07-03
Information query
IPC分类: