Invention Grant
US08828822B2 Method for fabricating semiconductor device with reduced Miller capacitance
有权
具有减小的米勒电容的半导体器件的制造方法
- Patent Title: Method for fabricating semiconductor device with reduced Miller capacitance
- Patent Title (中): 具有减小的米勒电容的半导体器件的制造方法
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Application No.: US13628055Application Date: 2012-09-27
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Publication No.: US08828822B2Publication Date: 2014-09-09
- Inventor: Yung-Fa Lin , Chia-Hao Chang
- Applicant: Anpec Electronics Corporation
- Applicant Address: TW Hsinchu Science Park, Hsin-Chu
- Assignee: Anpec Electronics Corporation
- Current Assignee: Anpec Electronics Corporation
- Current Assignee Address: TW Hsinchu Science Park, Hsin-Chu
- Agent Winston Hsu; Scott Margo
- Priority: TW101129913A 20120817
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
A method for fabricating a semiconductor transistor device. An epitaxial layer is grown on a semiconductor substrate. A gate trench is formed in the epitaxial layer. A spacer is formed on a sidewall of the gate trench. A recess is formed at the bottom of the gate trench. A thermal oxidation process is performed to form an oxide layer in the recess. The oxide layer completely fills the recess. The spacer is then removed. A gate oxide layer is formed on the exposed sidewall of the gate trench. A gate is then formed into the gate trench.
Public/Granted literature
- US20140051220A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH REDUCED MILLER CAPACITANCE Public/Granted day:2014-02-20
Information query
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