Invention Grant
- Patent Title: Pattern forming methods and semiconductor device manufacturing method
- Patent Title (中): 图案形成方法和半导体器件制造方法
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Application No.: US13767168Application Date: 2013-02-14
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Publication No.: US08828747B2Publication Date: 2014-09-09
- Inventor: Hironobu Sato
- Applicant: Kabushiki Kaisha Toshiba
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2012-172158 20120802
- Main IPC: H01L21/66
- IPC: H01L21/66 ; H01L21/31 ; B05D1/36

Abstract:
According to one embodiment, a pattern forming method includes forming a self-assembled material on a plurality of first patterns, forming a plurality of second patterns by heating the self-assembled material and causing microphase separation of the self-assembled material, the second patterns corresponding to the first patterns, and calculating positional deviations of respective positions of the second patterns from positions of the corresponding first patterns. When at least one of the positional deviations is larger than a predetermined value, the self-assembled material is adjusted.
Public/Granted literature
- US20140038318A1 PATTERN FORMING METHODS AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD Public/Granted day:2014-02-06
Information query
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