A signal processing circuit includes a first multiplying unit which multiplies a first signal including a first frequency by a second signal including a second frequency and outputs a third signal, a second multiplying unit which multiplies the first signal by a fourth signal of a second frequency with phase lagging of a first phase difference relative to the second signal and outputs a fifth signal, a third multiplying unit which multiplies the first signal by the sixth signal of the second frequency with phase lagging of a second phase difference relative to the second signal and outputs a seventh signal, a first adding unit which adds the third signal, the fifth signal and the seventh signal respectively weighted and a signal generating unit which controls the first and the second phase difference based on a control signal and outputs the second, the fourth and the sixth signal.