Invention Grant
US08797790B1 Memory elements with soft error upset immunity 有权
内存元件具有软错误的不安定性

Memory elements with soft error upset immunity
Abstract:
Memory elements are provided that exhibit immunity to soft error upset events when subjected to radiation strikes such as high-energy atomic particle strikes. Each memory element may each have four inverter-like transistor pairs that form a bistable element, a pair of address transistors, and a pair of relatively weak transistors connected between two of the inverters that create a common output node which is resistant to rapid changes to its state. The transistors may be connected in a pattern that forms a bistable memory element that is resistant to soft error upset events due to radiation strikes. Data may be loaded into and read out of the memory element using the address transistor pair.
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