A differential delay line includes a series connection of a plurality of differential delay stages. Each differential delay stage includes a first delay element and a second delay element. The first delay element has a first input, a second input and an output. The second delay element has a first input, a second input and an output. The output of the first delay element of an n-th differential delay stage of the plurality of differential delay stages is coupled to an input of the second delay element of an (n+m)-th differential delay stage of the plurality of differential delay stages, wherein m is an even natural number larger than or equal to two.