Invention Grant
- Patent Title: Memory circuit
- Patent Title (中): 存储电路
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Application No.: US13356749Application Date: 2012-01-24
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Publication No.: US08773906B2Publication Date: 2014-07-08
- Inventor: Takuro Ohmaru
- Applicant: Takuro Ohmaru
- Applicant Address: JP Atsugi-shi, Kanagawa-ken
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP Atsugi-shi, Kanagawa-ken
- Agency: Fish & Richardson P.C.
- Priority: JP2011-015595 20110127; JP2011-108902 20110514
- Main IPC: G11C14/00
- IPC: G11C14/00 ; G11C5/14 ; G11C11/34 ; G11C11/41 ; H01L29/788 ; H01L29/792

Abstract:
The present invention provides a memory circuit in which, while the power is not supplied, a data signal that has been held in a memory section corresponding to a volatile memory can be held in a capacitor in a memory section corresponding to a nonvolatile memory. In the nonvolatile memory section, a transistor whose channel is formed in an oxide semiconductor layer allows a signal to be held in the capacitor for a long period. Thus, the memory circuit can hold a logic state (data signal) even while the power supply is stopped. A potential applied to a gate of the transistor whose channel is formed in an oxide semiconductor layer is raised by a booster circuit provided between a wiring for carrying power supply potential and the gate of the transistor, allowing a data signal to be held even by one power supply potential without malfunction.
Public/Granted literature
- US20120195122A1 MEMORY CIRCUIT Public/Granted day:2012-08-02
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