Invention Grant
- Patent Title: Activate signal generating circuit and semiconductor memory device
- Patent Title (中): 激活信号发生电路和半导体存储器件
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Application No.: US13728727Application Date: 2012-12-27
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Publication No.: US08767504B2Publication Date: 2014-07-01
- Inventor: Shoichiro Kawashima
- Applicant: Fujistu Semiconductor Limited
- Applicant Address: JP Yokohama
- Assignee: Fujitsu Semiconductor Limited
- Current Assignee: Fujitsu Semiconductor Limited
- Current Assignee Address: JP Yokohama
- Agency: Arent Fox LLP
- Priority: JP2012-035376 20120221
- Main IPC: G11C8/00
- IPC: G11C8/00 ; G11C8/18

Abstract:
An activate signal generating circuit, to which a first and a second activate signals which are pulse signals are applied, and which generates an internal activate signal, has a first delay element. The internal activate signal is activated based on timings of front (active transient) edges of the first and second activate signals. When a timing of a rear (inactive transient) edge of the first activate signal is earlier than a timing of a rear edge of the second activate signal, the internal activate signal goes inactivate based on the timing of the rear edge of the first activate signal, and when the timing of the rear edge of the first activate signal is later than the timing of the rear edge of the second activate signal, the internal activate signal goes inactivate after a predetermined delay time based on a delay time of the first delay element.
Public/Granted literature
- US20130215664A1 ACTIVATE SIGNAL GENERATING CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2013-08-22
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