Invention Grant
- Patent Title: Semiconductor memory device and method for inspecting the same
- Patent Title (中): 半导体存储器件及其检测方法
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Application No.: US13235967Application Date: 2011-09-19
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Publication No.: US08767443B2Publication Date: 2014-07-01
- Inventor: Toshihiko Saito
- Applicant: Toshihiko Saito
- Applicant Address: JP Atsugi-shi, Kanagawa-ken
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP Atsugi-shi, Kanagawa-ken
- Agency: Fish & Richardson P.C.
- Priority: JP2010-212179 20100922
- Main IPC: G11C11/24
- IPC: G11C11/24

Abstract:
When the threshold voltage Vth of the transistor in the memory cell is within the allowable range is determined, a memory cell which does not have sufficient data retention characteristics is eliminated. In order to eliminate such a memory cell, the potential of a gate of the transistor is kept at an appropriate potential VGM and the potential of a drain of the transistor is set higher than or equal to VGM. When data is written to the memory cell in this state, the potential of a source of the transistor is expressed as a formula including the threshold voltage Vth, (VGM−Vth). By comparison between the level of the potential and the level of a reference potential, whether the threshold voltage Vth is within the allowable range can be determined.
Public/Granted literature
- US20120069634A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR INSPECTING THE SAME Public/Granted day:2012-03-22
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