Invention Grant
US08707127B2 Configurable source based/requestor based error detection and correction for soft errors in multi-level cache memory to minimize CPU interrupt service routines
有权
可配置的基于源/请求者的错误检测和纠正多级缓存中的软错误，以最大限度地减少CPU中断服务程序
- Patent Title: Configurable source based/requestor based error detection and correction for soft errors in multi-level cache memory to minimize CPU interrupt service routines
- Patent Title (中): 可配置的基于源/请求者的错误检测和纠正多级缓存中的软错误，以最大限度地减少CPU中断服务程序
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Application No.: US13243335Application Date: 2011-09-23
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Publication No.: US08707127B2Publication Date: 2014-04-22
- Inventor: Jonathan (Son) Hung Tran , Abhijeet Ashok Chachad , Raguram Damodaran , Krishna Chaithanya Gurram
- Applicant: Jonathan (Son) Hung Tran , Abhijeet Ashok Chachad , Raguram Damodaran , Krishna Chaithanya Gurram
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Robert D. Marshall, Jr.; W. James Brady; Frederick J. Telecky, Jr.
- Main IPC: H03M13/00
- IPC: H03M13/00
Abstract:
This invention is a memory system with parity generation which selectively forms and stores parity bits of corresponding plural data sources. The parity generation and storage depends upon the state of a global suspend bit and a global enable bit, and parity detection/correction corresponding to each data source.
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