Invention Grant
- Patent Title: Predicting routability of integrated circuits
- Patent Title (中): 预测集成电路的可布线性
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Application No.: US12643528Application Date: 2009-12-21
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Publication No.: US08694944B1Publication Date: 2014-04-08
- Inventor: Sze Huey Soo , Thow Pang Chong , Boon Jin Ang , Kar Keng Chua
- Applicant: Sze Huey Soo , Thow Pang Chong , Boon Jin Ang , Kar Keng Chua
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agency: Mauriel Kapouytian Woods LLP
- Agent Michael Mauriel
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Methods, computer program products, and systems are disclosed associated with calculating a routability metric for a second IC design using inputs from the compilation to a first IC design. The first and second IC designs are alternative implementation options for a user circuit design, such as FPGA and structured ASIC options. Information about user design demands on routing resources of one IC design are considered along with information about the projected supply of routing resources in another IC design, to produce a routing metric. The routing metric may be mapped to a degree of difficulty indicator, and either may be used to condition a compile of the user circuit to the second IC design or be used in other ways.
Information query