Invention Grant
US08694926B2 Techniques for checking computer-aided design layers of a device to reduce the occurrence of missing deck rules
有权
用于检查设备的计算机辅助设计层以减少缺失甲板规则的发生的技术
- Patent Title: Techniques for checking computer-aided design layers of a device to reduce the occurrence of missing deck rules
- Patent Title (中): 用于检查设备的计算机辅助设计层以减少缺失甲板规则的发生的技术
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Application No.: US13484022Application Date: 2012-05-30
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Publication No.: US08694926B2Publication Date: 2014-04-08
- Inventor: Douglas M Reber , Mehul D. Shroff , Edward O Travis
- Applicant: Douglas M Reber , Mehul D. Shroff , Edward O Travis
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agency: Yudell Isidore Ng Russell PLLC
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
A technique for computer-aided design layer checking of an integrated circuit design includes generating a representation of a device (e.g., a parameterized cell). Computer-aided design (CAD) layers are sequentially removed from the parameterized cell and a determination is made as to whether expected errors are detected or missed by an associated deck. The associated deck is then modified to detect the expected errors that are missed.
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