A circuit and a method for parallel perforation in rate matching can adopt three selector arrays and three register groups. The first selector array is configured to remove null bits in input data and output the remaining data to the first register group; the second selector array is configured to combine the first register group and the third register group and then output the combined data to the second register group; during the combination, the valid data in the third register group are preferentially selected, and then the data in the first register group are selected; Further, the third selector array is configured to output remaining valid data in the first selector group to the third register group if the valid data in the first selector group are not used out while combining the first register group and the third register group by the second selector array.