Invention Grant
US08694843B2 Clock control of pipelined memory for improved delay fault testing
有权
流水线内存的时钟控制，用于改进延迟故障测试
- Patent Title: Clock control of pipelined memory for improved delay fault testing
- Patent Title (中): 流水线内存的时钟控制，用于改进延迟故障测试
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Application No.: US13198324Application Date: 2011-08-04
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Publication No.: US08694843B2Publication Date: 2014-04-08
- Inventor: Ramakrishnan Venkatasubramanian , Sumant Kale , Abhijeet Ashok Chachad
- Applicant: Ramakrishnan Venkatasubramanian , Sumant Kale , Abhijeet Ashok Chachad
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent John R. Pessetto; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: G01R31/28
- IPC: G01R31/28
Abstract:
In an embodiment of the invention, a pipelined memory bank is tested by scanning test patterns into an integrated circuit. Test data is formed from the test patterns and shifted into a scan-in chain in the pipelined memory bank. The test data in the scan-in chain is launched into the inputs of the pipelined memory bank during a first clock cycle. Data from the outputs of the pipelined memory bank is captured in a scan-out chain during a second cycle where the time between the first and second clock cycles is equal to or greater than the read latency of the memory bank.
Public/Granted literature
- US20130036337A1 Clock Control of Pipelined Memory for Improved Delay Fault Testing Public/Granted day:2013-02-07
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