Invention Grant
US08694812B2 Memory calibration method and apparatus for power reduction during flash operation
有权
闪存操作期间功率降低的存储器校准方法和设备
- Patent Title: Memory calibration method and apparatus for power reduction during flash operation
- Patent Title (中): 闪存操作期间功率降低的存储器校准方法和设备
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Application No.: US13012299Application Date: 2011-01-24
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Publication No.: US08694812B2Publication Date: 2014-04-08
- Inventor: Rex Weldon Vedder , Bradford Edwin Golson , Michael Joseph Peters
- Applicant: Rex Weldon Vedder , Bradford Edwin Golson , Michael Joseph Peters
- Applicant Address: US CO Longmont
- Assignee: Dot Hill Systems Corporation
- Current Assignee: Dot Hill Systems Corporation
- Current Assignee Address: US CO Longmont
- Agent Thomas J. Lavan
- Main IPC: G06F1/00
- IPC: G06F1/00

Abstract:
A method for providing reduced power consumption in a computer memory system is provided. The method includes calibrating, by a processor, a volatile memory of the computer memory system at a first and a second operating speed, where the second operating speed is higher than the first operating speed. The method also includes operating, by a memory controller coupled to the processor and the volatile memory, the volatile memory at the second operating speed if a main power source provides power to the computer memory system. The method further includes operating, by the memory controller, the volatile memory at the first operating speed if a backup power source provides power to the memory controller and the volatile memory. The backup power source provides power to the memory controller and the volatile memory when there is a loss of main power to the computer memory system.
Public/Granted literature
- US20110239021A1 Memory calibration method and apparatus for power reduction during flash operation Public/Granted day:2011-09-29
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