Invention Grant
- Patent Title: Wear leveling for erasable memories
- Patent Title (中): 可擦写记忆的磨损均衡
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Application No.: US13142487Application Date: 2008-12-30
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Publication No.: US08694718B2Publication Date: 2014-04-08
- Inventor: Massimo Iaculo , Ornella Vitale , Antonino Pollio
- Applicant: Massimo Iaculo , Ornella Vitale , Antonino Pollio
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dorsey & Whitney LLP
- International Application: PCT/IT2008/000817 WO 20081230
- International Announcement: WO2010/076829 WO 20100708
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G11C16/04
Abstract:
In accordance with some embodiments, wear leveling may be done based on the difference in age of discarded blocks and engaged blocks. Data is moved to an older discarded block from a younger engaged block. Two wear leveling bits may be used for each logical block, such that the wear leveling bits are used in alternating cycles.
Public/Granted literature
- US20110271030A1 Wear Leveling For Erasable Memories Public/Granted day:2011-11-03
Information query
