Invention Grant
- Patent Title: AC coupled clock receiver with common-mode noise rejection
- Patent Title (中): 交流耦合时钟接收器具有共模噪声抑制
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Application No.: US12497485Application Date: 2009-07-02
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Publication No.: US08693557B1Publication Date: 2014-04-08
- Inventor: Liang Leon Zhang , Alejandro F. Gonzalez
- Applicant: Liang Leon Zhang , Alejandro F. Gonzalez
- Applicant Address: US CA San Jose
- Assignee: Integrated Device Technology inc.
- Current Assignee: Integrated Device Technology inc.
- Current Assignee Address: US CA San Jose
- Agency: Glass & Associates
- Agent Kenneth Glass; Stanley J. Pawlik
- Main IPC: H04L27/00
- IPC: H04L27/00

Abstract:
A clock receiver includes a capacitive coupling circuit for filtering out direct-current voltages from a differential clock signal. In this way, the capacitive coupling circuit rejects common-mode noise in the differential clock signal. The clock receiver also includes a bias circuit for establishing a bias voltage in the differential clock signal and a differential amplifier for amplifying the differential clock signal. Further, the differential amplifier generate a feedback differential clock signal and provides the feedback differential clock signal to the bias circuit for further rejecting common-mode noise in the differential clock signal. The feedback differential clock signal functions as a negative feedback signal for rejecting common-mode noise in the differential clock signal and as a positive feedback signal for amplifying the differential clock signal. In some embodiments, the clock receiver includes a capacitive coupling circuit with a cut-off frequency above the frequency of the differential clock signal.
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