A semiconductor memory includes first and second memory storage latches each including first and second ports. A first pair of bit lines is coupled to the first ports, and a second pair of bit lines is coupled to the second ports. The first and second pairs of bit lines are twisted between the first and second memory storage latches. A first sense amplifier is coupled to the first pair of bit lines for outputting data, and a second sense amplifier is coupled to the second pair of bit lines for outputting an intermediate data signal. Output logic circuitry is coupled to an output of the second sense amplifier and is configured to output data based on the intermediate data signal and a control signal that identifies if the data is being read from the first memory storage latch or from the second memory storage latch.