Invention Grant
- Patent Title: Non-volatile semiconductor memory device
- Patent Title (中): 非易失性半导体存储器件
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Application No.: US13597498Application Date: 2012-08-29
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Publication No.: US08693254B2Publication Date: 2014-04-08
- Inventor: Toshifumi Hashimoto
- Applicant: Toshifumi Hashimoto
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2012-016105 20120130
- Main IPC: G11C11/34
- IPC: G11C11/34

Abstract:
A limiter circuit compares a voltage of a control gate line and a set voltage, thereby switching the logic of a flag signal. A booster circuit starts or stops its operation according to the logic of the flag signal. A leak reference circuit has a function of leaking a leak reference current from the control gate line. A counter generates a first count value by counting the number of times the flag signal logic changes in a condition that a word-line transfer transistor is rendered non-conductive and a leak reference circuit is driven, while the counter generates a second count value by counting the number of times the flag signal logic changes in a condition that the word-line transfer transistor is rendered conductive and the leak reference circuit is undriven. A comparator compares the first count value and the second count value.
Public/Granted literature
- US20130194868A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2013-08-01
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