A clock phase measurement circuit comprises a selector circuit operable to inject one of a first analog clock signal or a second analog clock signal into a signal path configured to carry an analog data signal, so that the injected analog clock signal replaces the data signal. An Analog to Digital Converter (ADC) converts the injected analog clock signal to a digital clock signal. A counter selects a time, using the second analog clock signal, to determine at least one of a phase or a magnitude of the digital clock signal. A measurement circuit determines at least one of the phase or the magnitude of the digital clock signal for at least one frequency at the selected time.