Invention Grant
- Patent Title: Methods of forming recessed channel array transistors and methods of manufacturing semiconductor devices
- Patent Title (中): 形成凹槽阵列晶体管的方法和制造半导体器件的方法
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Application No.: US13151494Application Date: 2011-06-02
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Publication No.: US08691649B2Publication Date: 2014-04-08
- Inventor: Tai-Su Park , Jung-Sup Oh , Gun-Joong Lee , Jung-Soo An , Dong-Kyu Lee , Jung-Geun Park , Jeong-Do Ryu , Dong-Chan Kim , Seong-Hoon Jeong , Si-Young Choi , Yu-Gyun Shin , Jong-Ryeol Yoo , Jong-Hoon Kang
- Applicant: Tai-Su Park , Jung-Sup Oh , Gun-Joong Lee , Jung-Soo An , Dong-Kyu Lee , Jung-Geun Park , Jeong-Do Ryu , Dong-Chan Kim , Seong-Hoon Jeong , Si-Young Choi , Yu-Gyun Shin , Jong-Ryeol Yoo , Jong-Hoon Kang
- Applicant Address: KR
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR
- Agency: Myers Bigel Sibley & Sajovec, PA
- Priority: KR10-2008-0092483 20080922; KR10-2009-0041222 20090512; KR10-2010-0053468 20100607
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
In methods of manufacturing a recessed channel array transistor, a recess may be formed in an active region of a substrate. A plasma oxidation process may be performed on the substrate to form a preliminary gate oxide layer on an inner surface of the recess and an upper surface of the substrate. Moistures may be absorbed in a surface of the preliminary gate oxide layer to form a gate oxide layer. A gate electrode may be formed on the gate oxide layer to fill up the recess. Source/drain regions may be formed in an upper surface of the substrate at both sides of the gate electrode. Thus, the oxide layer may have a uniform thickness distribution and a dense structure.
Public/Granted literature
- US20110237037A1 Methods of Forming Recessed Channel Array Transistors and Methods of Manufacturing Semiconductor Devices Public/Granted day:2011-09-29
Information query
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