Invention Grant
- Patent Title: Semiconductor package structure and manufacturing method thereof
- Patent Title (中): 半导体封装结构及其制造方法
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Application No.: US13647406Application Date: 2012-10-09
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Publication No.: US08691630B2Publication Date: 2014-04-08
- Inventor: Yu-Tang Pan , Shih-Wen Chou
- Applicant: ChipMOS Technologies Inc.
- Applicant Address: TW Hsinchu
- Assignee: ChipMOS Technologies Inc.
- Current Assignee: ChipMOS Technologies Inc.
- Current Assignee Address: TW Hsinchu
- Agency: Jianq Chyun IP Office
- Priority: TW100144388A 20111202
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A method of manufacturing a semiconductor package structure is provided. A heat-conductive block is adhered to a portion of a second surface of a conductive substrate via a first adhesive layer. An opening is formed by performing a half-etching process on a first surface of the conductive substrate. The remaining conductive substrate is patterned to form leads and expose a portion of the heat-conductive block. Each lead has a first portion and a second portion. A thickness of the first portion is greater than a thickness of the second portion. A first lower surface of the first portion and a second lower surface of the second portion are coplanar. A chip is disposed on the exposed portion of the heat-conductive block and electrically connected to the second portions of the leads. A first bottom surface of the heat-conductive block and a second bottom surface of a molding compound are coplanar.
Public/Granted literature
- US20130140686A1 SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF Public/Granted day:2013-06-06
Information query
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