Invention Grant
- Patent Title: Method of manufacturing semiconductor device, manufacturing program, and manufacturing apparatus
- Patent Title (中): 制造半导体装置的方法，制造程序和制造装置
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Application No.: US13226152Application Date: 2011-09-06
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Publication No.: US08691628B2Publication Date: 2014-04-08
- Inventor: Yasuo Tane , Yukio Katamura , Atsushi Yoshimura , Fumihiro Iwami
- Applicant: Yasuo Tane , Yukio Katamura , Atsushi Yoshimura , Fumihiro Iwami
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2010-275988 20101210
- Main IPC: H01L21/00
- IPC: H01L21/00
Abstract:
According to one embodiment, a method of manufacturing a semiconductor device, a bonding layer is formed on a first surface of a chip region of a semiconductor wafer. Semiconductor chips are singulated along a dicing region. The semiconductor chips are stacked stepwise via the bonding layer. In formation of the bonding layer of the semiconductor chip, in at least a part of a first region of the first surface not in contact with the other semiconductor chip in a stacked state, a projected section where the bonding layer is formed thicker than the bonding layer in a second region that is in contact with the other semiconductor chip is provided.
Public/Granted literature
- US20120149151A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, MANUFACTURING PROGRAM, AND MANUFACTURING APPARATUS Public/Granted day:2012-06-14
Information query
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