Invention Grant
- Patent Title: Optimizing designs of integrated circuits
- Patent Title (中): 优化集成电路设计
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Application No.: US13007579Application Date: 2011-01-14
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Publication No.: US08689165B2Publication Date: 2014-04-01
- Inventor: Jovanka Ciric Vujkovic , Kenneth S. McElvain
- Applicant: Jovanka Ciric Vujkovic , Kenneth S. McElvain
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Agent Judith A. Szepesi
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Methods and systems for optimizing and/or designing integrated circuits. One exemplary method includes routing, as part of a process of designing an integrated circuit (IC), connections on a representation of the IC using a first set of wiring resources and marking wiring resources as used once the wiring resources within the first set have been used for routing and routing, using a second set of wiring resources in the representation, connections on the IC without checking whether wiring resources within the second set have been previously used to route connections, wherein wiring resources in the second set differ, on average, in physical size, from wiring resources in the first set. Other methods and systems for optimizing and/or designing ICs are also described, and machine-readable media containing executable program instructions which cause systems to perform one or more of these methods are also described.
Public/Granted literature
- US20110113399A1 Methods and Systems for Optimizing Designs of Integrated Circuits Public/Granted day:2011-05-12
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