A memory module for operating with a system memory controller comprises a plurality of data ports, a plurality of memory devices organized in ranks, and a plurality of data handlers. Each respective data handler is coupled to a respective set of data ports of the plurality of data ports and to a respective set of memory devices of the plurality of memory devices. Each set of memory devices include at least one memory device from each rank. In a normal mode, each respective data handler is configured to provide write data received from the system memory controller via the respective data ports to the respective set of memory devices. In a test mode, each respective data handler is configured to provide test data generated in the respective data handler to the respective set of memory devices.