One embodiment relates to an interpolator-based clock and data recovery (iCDR) circuit. The iCDR circuit includes an automatic gain control circuit arranged to generate an interpolation jump size signal when a targeted sampling detection signal is asserted. The targeted sampling detection signal may be asserted when sampling by the phase detector of the iCDR circuit is within a targeted range. The interpolation jump size signal may indicate a number of phase steps to shift an interpolation state signal if a jump is indicated by a filtered feedback signal. Other embodiments and features are also disclosed.