A semiconductor memory device pertaining to the present invention includes a plurality of memory macros having memory cells and memory peripheral circuits which drive the memory cells; first power supply switches which control power supply to the memory cells; and a second power supply switch which controls power supply to the memory peripheral circuits. The first power supply switches are located within the memory macros, respectively, and provided between a power supply line feeding power to the memory cells and the memory cells. The second power supply switch is located outside the memory macros and provided between the power supply line and a common power supply wiring for the memory peripheral circuits in the plurality of memory macros.