Invention Grant
US08687436B2 Increasing efficiency of memory accesses by selectively introducing a relative delay between the time that write addresses are provided to the memory and the time that write data is provided to the memory
失效
通过在写入地址被提供给存储器的时间和向存储器提供写入数据的时间之间选择性地引入相对延迟来提高存储器访问的效率
- Patent Title: Increasing efficiency of memory accesses by selectively introducing a relative delay between the time that write addresses are provided to the memory and the time that write data is provided to the memory
- Patent Title (中): 通过在写入地址被提供给存储器的时间和向存储器提供写入数据的时间之间选择性地引入相对延迟来提高存储器访问的效率
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Application No.: US13442382Application Date: 2012-04-09
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Publication No.: US08687436B2Publication Date: 2014-04-01
- Inventor: J. Thomas Pawlowski
- Applicant: J. Thomas Pawlowski
- Applicant Address: US NJ Jersey City
- Assignee: Round Rock Research, LLC
- Current Assignee: Round Rock Research, LLC
- Current Assignee Address: US NJ Jersey City
- Agency: Lerner, David, Littenberg, Krumholz & Mentlik, LLP
- Main IPC: G06F12/00
- IPC: G06F12/00
Abstract:
Systems and methods for reducing delays between successive write and read accesses in multi-bank memory devices are provided. Computer circuits modify the relative timing between addresses and data of write accesses, reducing delays between successive write and read accesses. Memory devices that interface with these computer circuits use posted write accesses to effectively return the modified relative timing to its original timing before processing the write access.
Public/Granted literature
- US20120198194A1 Multi-Bank Memory Accesses Using Posted Writes Public/Granted day:2012-08-02
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