Invention Grant
- Patent Title: Semiconductor device having plural wiring layers
- Patent Title (中): 具有多个布线层的半导体装置
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Application No.: US13298995Application Date: 2011-11-17
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Publication No.: US08686567B2Publication Date: 2014-04-01
- Inventor: Kiyotaka Endo , Kazuteru Ishizuka , Hiroki Fujisawa
- Applicant: Kiyotaka Endo , Kazuteru Ishizuka , Hiroki Fujisawa
- Priority: JP2010-258144 20101118
- Main IPC: H01L23/52
- IPC: H01L23/52 ; H01L23/48 ; H01L29/40

Abstract:
A semiconductor device includes a lower wiring layer, having signal lines and power supply lines extending in a Y-direction; an upper wiring layer having signal lines and power supply lines extending in an X-direction; via conductors provided in first overlap regions where corresponding signal lines overlap each other; and via conductors provided in second overlap regions where corresponding power supply lines overlap each other. The width in the X-direction of the first regions is wider than the widths in the X-direction of the second regions. Therefore, in the first regions, a plurality of via conductors can be provided. Moreover, the power supply lines are divided in the Y-direction to avoid interference with the first regions. On a plurality of lower-layer lines, two vias are placed at a minimum pitch containing one via.
Public/Granted literature
- US20120126422A1 SEMICONDUCTOR DEVICE HAVING PLURAL WIRING LAYERS Public/Granted day:2012-05-24
Information query
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