Invention Grant
- Patent Title: Stacked chip assembly having vertical vias
- Patent Title (中): 具有垂直通孔的堆叠式芯片组件
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Application No.: US12883431Application Date: 2010-09-16
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Publication No.: US08686565B2Publication Date: 2014-04-01
- Inventor: Vage Oganesian , Belgacem Haba , Ilyas Mohammed , Craig Mitchell , Piyush Savalia
- Applicant: Vage Oganesian , Belgacem Haba , Ilyas Mohammed , Craig Mitchell , Piyush Savalia
- Applicant Address: US CA San Jose
- Assignee: Tessera, Inc.
- Current Assignee: Tessera, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Lerner, David, Littenberg, Krumholz & Mentlik, LLP
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L21/50
Abstract:
An assembly and method of making same are provided. The assembly can be formed by stacking a first semiconductor element atop a second semiconductor element and forming an electrically conductive element extending through openings of the semiconductor elements. The openings may be staged. The conductive element can conform to contours of the interior surfaces of the openings and can electrically connect conductive pads of the semiconductor elements. A dielectric region can be provided at least substantially filling the openings of the semiconductor elements, and the electrically conductive element can extend through an opening formed in the dielectric region.
Public/Granted literature
- US20120068352A1 STACKED CHIP ASSEMBLY HAVING VERTICAL VIAS Public/Granted day:2012-03-22
Information query
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