Invention Grant
- Patent Title: Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance
- Patent Title (中): 提高晶体管通道，减少浅沟槽隔离对晶体管性能的影响
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Application No.: US13221747Application Date: 2011-08-30
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Publication No.: US08686512B2Publication Date: 2014-04-01
- Inventor: Victor Moroz , Dipankar Pramanik , Xi-Wei Lin
- Applicant: Victor Moroz , Dipankar Pramanik , Xi-Wei Lin
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Haynes Beffel & Wolfeld LLP
- Agent Warren S. Wolfeld
- Main IPC: H01L27/092
- IPC: H01L27/092
Abstract:
Roughly described, transistor channel regions are elevated over the level of certain adjacent STI regions. Preferably the STI regions that are transversely adjacent to the diffusion regions are suppressed, as are STI regions that are longitudinally adjacent to N-channel diffusion regions. Preferably STI regions that are longitudinally adjacent to P-channel diffusions are not suppressed; preferably they have an elevation that is at least as high as that of the diffusion regions.
Public/Granted literature
- US20110309453A1 ELEVATION OF TRANSISTOR CHANNELS TO REDUCE IMPACT OF SHALLOW TRENCH ISOLATION ON TRANSISTOR PERFORMANCE Public/Granted day:2011-12-22
Information query
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