Invention Grant
US08686507B2 System and method for I/O ESD protection with floating and/or biased polysilicon regions
有权
具有浮置和/或偏置多晶硅区域的I / O ESD保护的系统和方法
- Patent Title: System and method for I/O ESD protection with floating and/or biased polysilicon regions
- Patent Title (中): 具有浮置和/或偏置多晶硅区域的I / O ESD保护的系统和方法
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Application No.: US11517546Application Date: 2006-09-06
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Publication No.: US08686507B2Publication Date: 2014-04-01
- Inventor: Ting Chieh Su , Min Chie Jeng , Chin Chang Liao , Jun Cheng Huang
- Applicant: Ting Chieh Su , Min Chie Jeng , Chin Chang Liao , Jun Cheng Huang
- Applicant Address: CN Shanghai
- Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
- Current Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
- Current Assignee Address: CN Shanghai
- Agency: Kilpatrick Townsend & Stockton LLP
- Priority: CN200610023162 20060104
- Main IPC: H01L23/62
- IPC: H01L23/62

Abstract:
A system and method for electrostatic discharge protection. The system includes a plurality of transistors. The plurality of transistors includes a plurality of gate regions, a plurality of source regions, and a plurality of drain regions. The plurality of source regions and the plurality of drain regions are located within an active area in a substrate, and the active area is adjacent to at least an isolation region in the substrate. Additionally, the system includes a polysilicon region. The polysilicon region is separated from the substrate by a dielectric layer, and the polysilicon region intersects each of the plurality of gate regions. At least a part of the polysilicon region is on the active area.
Public/Granted literature
- US20070164362A1 System and method for I/O ESD protection with floating and/or biased polysilicon regions Public/Granted day:2007-07-19
Information query
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