Invention Grant
- Patent Title: Trench filling method and method of manufacturing semiconductor integrated circuit device
- Patent Title (中): 半导体集成电路器件的沟槽填充方法和方法
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Application No.: US13594217Application Date: 2012-08-24
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Publication No.: US08685832B2Publication Date: 2014-04-01
- Inventor: Masahisa Watanabe
- Applicant: Masahisa Watanabe
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- Agency: Nath, Goldberg & Meyer
- Agent Jerald L. Meyer
- Priority: JP2011-183684 20110825
- Main IPC: H01L21/76
- IPC: H01L21/76

Abstract:
Provided is a trench filling method, which includes: forming a silicon oxide liner on a semiconductor substrate with trenches formed therein, the trenches including narrow-width portions having a first minimum isolation width and wide-width portions having a second minimum isolation width being wider than the first minimum isolation width; forming an oxidation-barrier film on the silicon oxide liner; forming a silicon liner on the oxidation-barrier film; filling the narrow-width portions with a first filling material; filling the wide-width portions with a second filling material; and oxidizing the silicon liner.
Public/Granted literature
- US20130052795A1 TRENCH FILLING METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Public/Granted day:2013-02-28
Information query
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