Invention Grant
US08685817B1 Metal gate structures for CMOS transistor devices having reduced parasitic capacitance
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具有减小的寄生电容的CMOS晶体管器件的金属栅极结构
- Patent Title: Metal gate structures for CMOS transistor devices having reduced parasitic capacitance
- Patent Title (中): 具有减小的寄生电容的CMOS晶体管器件的金属栅极结构
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Application No.: US13680560Application Date: 2012-11-19
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Publication No.: US08685817B1Publication Date: 2014-04-01
- Inventor: Jin Cai , Chengwen Pei , Robert R. Robison , Ping-Chuan Wang
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Michael LeStrange
- Main IPC: H01L21/8238
- IPC: H01L21/8238

Abstract:
A method of forming a field effect transistor (FET) device includes forming a gate structure over a substrate, the gate structure including a wide bottom portion and a narrow portion formed on top of the bottom portion; the wide bottom portion comprising a metal material and having a first width that corresponds substantially to a transistor channel length, and the narrow portion also including a metal material having a second width smaller than the first width.
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