A computer-readable recording medium stores a design support program that causes a computer to execute a process that includes generating based on a control flow graph conversion result for operation description information concerning a circuit-under-design, a first synthesis result according to which a time length of 1 clock cycle of the circuit-under-design is greater than or equal to a clock period in which the circuit-under-design operates; calculating based on the generated first synthesis result, first circuit scale information indicating a circuit scale of the circuit-under-design; acquiring a second synthesis result that is for the circuit-under-design and conforms to a timing constraint that is based on the control flow graph conversion result; calculating second circuit scale information indicating the circuit scale of the circuit-under-design, based on the generated second synthesis result; and outputting the calculated first circuit scale information and the calculated second circuit information.