A CPU (1) of an information processing apparatus (8) executes software stored in a DRAM (7). A watchdog timer (2) monitors the operation of the software. A hardware monitoring device (4) monitors the state of hardware provided in the information processing apparatus (8). Results of the monitoring are managed by a management LSI chip (3). A non-volatile memory (6) is where failure information is saved. If no watchdog toggles are received for a given period of time, the watchdog timer (2) notifies the CPU (1) with an NMI signal and starts the second round of time counting. The CPU (1) collects failure information from the management LSI (3). The CPU (1) is rebooted through cold reset when failure information collection is completed, and through hot reset when failure information collection is incomplete. In the case of hot reset, the CPU (1) collects failure information after rebooted.