Invention Grant
- Patent Title: Semiconductor chip and test method
- Patent Title (中): 半导体芯片和测试方法
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Application No.: US13474675Application Date: 2012-05-17
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Publication No.: US08667353B2Publication Date: 2014-03-04
- Inventor: Takashi Taya
- Applicant: Takashi Taya
- Applicant Address: JP
- Assignee: Lapis Semiconductor Co., Ltd.
- Current Assignee: Lapis Semiconductor Co., Ltd.
- Current Assignee Address: JP
- Agency: Rabin & Berdo. P.C.
- Priority: JP2011-111329 20110518
- Main IPC: G01R31/3181
- IPC: G01R31/3181 ; G01R31/40

Abstract:
A semiconductor chip having a functional block that performs a communication function includes an input circuit that supplies an oscillating test signal to the functional block, and a test circuit that detects the strength of an oscillating signal which the functional block outputs in response. A strength signal indicating the detected strength is output from the test circuit through an external terminal of the semiconductor chip to a test device. The test device evaluates the strength signal to decide whether an operating characteristic of the functional block is within a specified range. The strength information indicated by the strength signal is not affected by impedance on the signal transmission line between the semiconductor chip and the test device, so the test is not affected by impedance loss.
Public/Granted literature
- US20120297263A1 SEMICONDUCTOR CHIP AND TEST METHOD Public/Granted day:2012-11-22
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